In a scanning signal line drive circuit and a data signal line drive circuit of a matrix display device, shift registers are widely adopted to generate a scanning signal supplied to scanning signal lines and to control the timings for sampling voltages, which are supplied to respective data signal lines, from a video signal.
Meanwhile, being typified by a monitor panel of a video camera and a digital camera, a device, which can reproduce a mirror image which is a display image being inversed left to right or upside down in accordance with the orientation of an image display section, has been in practical use. In such a display device which can invert a display image, a bi-directional shift register which can switch the shifting direction (scanning direction) of data is used. With this bi-directional shift register, a mirror image can be reproduced only by switching the shifting direction, without storing a video signal.
For the meantime, the power consumption of an electronic circuit typified by an IC increases in proportion to the frequency, load-carrying capacity, and the second power of the voltage. For this reason, with regard to peripheral devices connected to the display device, such as a circuit generating a video signal supplied to the display device, and also with regard to the display device itself, there are increasing tendencies to further lower the drive voltages in order to reduce the power consumption.
Incidentally, there is a monolithic display device in which not only circuits of the display section but also a scanning signal line drive circuit and a data signal line drive circuit for driving the display section are formed on a substrate on which the display section is formed, in order to narrow down the frame circumscribing the display section and enlarge the size of the display section.
However, in the monolithic display device, particularly in a display device in which the scanning signal line drive circuit and the data signal line drive circuit are made up of polycrystalline silicon thin-film transistors, the difference between threshold voltages sometimes reaches several volts between the substrate or in one substrate. Thus, there is still a room for the reduction of the drive voltage.
For this reason, the scanning signal line drive circuit and the data signal line drive circuit driving the display section do not operate with a low-voltage signal supplied from the peripheral circuits which are driven by the low drive voltage, so that a level shifter which steps up the low-voltage signal to the operation voltage of these drive circuits is required.
FIG. 11 shows typical circuitry of such a level shifter. A level shifter 900 in the figure includes PMOS transistors 901, 903, 905, and 907 and NMOS transistors 902, 904, 906, and 908.
The PMOS transistors 901 and 903 are arranged such that the gate terminals are connected to a VSS level, the source terminals are connected to a VDD level, and the drain terminals are connected to the respective drain terminals of the NMOS transistors 902 and 904. The gate terminal and the drain terminal of the NMOS transistor 902 are connected to each other, and the source terminal of the NMOS transistor 902 is connected to the VSS level. The source terminal of the NMOS transistor 904 receives an input signal in (which is the target of stepping up). The PMOS transistors 901 and 903 and the NMOS transistors 902 and 904 constitute a level shifting section (level shifting means) 912.
The gate terminals of the PMOS transistor 905 and the NMOS transistor 906 are connected with a junction V2 of the drain terminal of the PMOS transistor 903 and the drain terminal of the NMOS transistor 904. The drain terminals of the PMOS transistor 905 and the NMOS transistor 906 are connected to each other. The source terminal of the PMOS transistor is connected to the VDD level, while the source terminal of the NMOS transistor 906 is connected to the VSS level. The PMOS transistor 905 and the NMOS transistor 906 constitute an inverter 910.
The junction of the drain terminal of the PMOS transistor 905 and the drain terminal of the NMOS transistor 906 functions as an output terminal of the inverter 910, and this output terminal is connected to the gate terminals of the PMOS transistor 907 and the NMOS transistor 908. The drain terminals of the PMOS transistor 907 and the NMOS transistor 908 are connected to each other. The source terminal of the PMOS transistor 907 is connected to the VDD level, while the source terminal of the NMOS transistor 908 is connected to the VSS level. The PMOS transistor 907 and the NMOS transistor 908 constitute an inverter 911 of the second stage. The junction of the drain terminal of the PMOS transistor 907 and the drain terminal of the NMOS transistor 908 function as an output terminal of the inverter 911, and an output signal out is outputted from this output terminal.
In the above-described level shifter, the gate terminal of the PMOS transistor 901 is connected to the VSS level, so that the PMOS transistor 901 turns ON and the VDD level appears at the drain terminal of the PMOS transistor 901. Since this drain terminal is also connected to the gate terminal of the NMOS transistor 902, the NMOS transistor 902 also turns ON. As a result, the junction V1 of the PMOS transistor 901 and the NMOS transistor 902 has a constant voltage between the VDD level and the VSS level, and this constant voltage is used as a bias voltage of the NMOS transistor 904.
The PMOS transistor 903 turns ON as the gate terminal thereof is connected to the VSS level, and the drain terminal of the PMOS transistor 903 is at the VDD level. The NMOS transistor 904 also turns ON as the gate terminal thereof receives the bias voltage appearing at the junction V1. As a result, a voltage at the output terminal V2 of the level shifting section 912, the output terminal V2 being identical with the junction V2 of the PMOS transistor 903 and the NMOS transistor 904, is determined by a voltage of the input signal in supplied from the input terminal. Assuming that the input signal in at the VSS level is LOW and the input signal in at the VCC level (VCC<VDD) is HIGH, the junction V2 is at a constant voltage Vlow which is between the VDD and VSS levels, when the input signal in is LOW, while the junction V2 is at a constant voltage Vhigh which is between the VDD and VCC levels, when the input signal in is HIGH.
The inverter 910 made up of the PMOS transistor 905 and the NMOS transistor 906 has a threshold between the voltages Vlow and Vhigh. When the voltage at the junction V2, which is supplied to the inverter 910, is Vlow, the PMOS transistor 905 turns ON so that the junction V3 equivalent to the output terminal of the PMOS transistor 905 is at the VDD level. In the meantime, when the voltage at the junction V2 is Vhigh, the NMOS transistor 906 turns ON so that the junction V3 is at the VSS level.
The inverter 911 made up of the PMOS transistor 907 and the NMOS transistor 908 is a conventional inverter. When the voltage at the junction V3, which is supplied to the inverter 911, is at the VDD level, the NMOS transistor 908 turns ON so that the output signal out therefrom is at the VSS level. Meanwhile, when the junction V3 is at the VSS level, the PMOS transistor 907 turns ON so that the output signal out therefrom is at the VDD level.
In summary, when the input signal in supplied to the level shifting section 912 is LOW (VSS level), the high-voltage output signal out is at the VSS level. When the low-voltage input signal in is HIGH (VCC level), the high-voltage output signal out is at the VDD level. In this manner, the low-voltage input signal in is level-shifted to the high-voltage output signal out.
Incidentally, in the foregoing level shifter 900, there is a current path from a VDD-level power source on the HIGH side to a VSS-level power source on the LOW side, and a current termed a stationary current always flows in the current path. More specifically, the stationary current flows from the PMOS transistor 901 to the NMOS transistor 902, thereby causing the junction V1 to have a predetermined voltage, and generating the bias voltage of the NMOS transistor 904. As a result, the level shifting section 912 operates. However, although such a stationary current is required for level-shifting the low-voltage input signal in to the high-voltage output signal out, the stationary current unnecessarily flows even when the level shifting is not carried out, thereby unnecessarily increasing the power consumption.
To reduce the unnecessary power consumption in the shift register, Japanese Laid-Open Patent Application No. 2000-322020 (Tokukai 2000-322020; published on Nov. 24, 2000) teaches as follows: Among level shifters which step up a start signal and are provided at the respective sides of a bi-directional shift register, one of these level shifters which does not correspond to the present shifting direction is not used, so that the path of a stationary current in that level shifter not being used is blocked.
In a panel adopting a bi-directional shift register which can switch the shifting direction, a start signal which starts the bi-directional shift register has to be supplied from one of two sides of the bi-directional shift register. For this reason, level shifters for level-shifting the start signal may be provided on the both sides of the bi-directional shift register. However, the shift direction is not frequently switched, and hence one of the level shifters is kept unused until the shift direction is changed. The Japanese document teaches the elimination of unnecessary power consumption in that unused level shifter.
Prior to the present application, the applicant of the present invention proposed a structure which can reduce the power consumption more than the above-described Japanese Laid-Open Patent Application No. 2000-322020, by eliminating the stationary current flowing in the level shifter which level-shifts the start signal, during the operating time of that shift register (Japanese Patent Application No. 2003-3284; applied on Jan. 9, 2004, corresponding to US2003/0179174A1; published in U.S.A. on Sep. 25, 2003).
This patent application found that, in Japanese Laid-Open Patent Application No. 2000-322020, the stationary current always flows in the level shifter being used and this current also results in unnecessary power consumption.
That is to say, the start signal requires the level shifting only when being switched from LOW to HIGH or HIGH to LOW, i.e. only when the bi-directional shift register starts. Therefore, the level shifting is unnecessary except these occasions. In other words, during the operating time of the bi-directional shift register, the level shifter which level-shifts the start signal is not required to operate, so that the stationary current of this shift register is not required. On this account, the power consumption is reduced in such a manner that the stationary current of the level shifter which level-shifts the start signal is eliminated during the operating time of the shift register.
Incidentally, when the start signal of the bi-directional shift register has a low voltage, a shifting direction switching signal which switches the shifting direction of the bi-directional shift register generally has a low voltage as well. For this reason, a level shifter for stepping up the shifting direction switching signal is provided as a matter of course. Therefore, unnecessary power consumption due to the above-described stationary current also occurs in this level shifter for the shifting direction switching signal.
In this behalf, the above-mentioned Japanese Laid-Open Patent Application No. 2000-322020 and US2003/0179174A1 both intend to reduce the power consumption in the level shifter which steps up the start signal, and hence neither of these documents mentions the reduction of the power consumption in the level shifter which steps up the shifting direction switching signal.
Furthermore, on the occasion of switching the shifting direction of the bi-directional shift register, it is necessary to change the shifting direction switching signal after the shifting in the bi-directional shift register finishes and before a start signal is newly supplied to the bi-directional shift register. This is because, if the shifting direction switching signal is changed during the signal shifting in the bi-directional shift register, the shifting direction is switched in the midst of the shifting operation, so that an image may not be properly reproduced.
To supply the shifting direction switching signal to the bi-directional shift register at a right timing, it is necessary to configure the logic in such a manner as to cause the shifting direction switching signal to be supplied after the signal shifting operation in the bi-directional shift register finishes and before the input of the next start signal, no matter when the shifting direction switching signal is changed.
The above-described problem of unnecessary power consumption in the level shifter for the shifting direction switching signal occurs not only in the level shifter for the shifting direction switching signal but also in level shifters for signals which are not frequently changed as in the case of the shifting direction, such as a resolution switching signal for switching resolutions and a driver switching signal for switching between a binary driver and an analog driver.